1. Field of the Invention
The present invention relates to the field of display, and in particular to an LCD display panel of dot inversion mode.
2. The Related Arts
The liquid crystal display (LCD) has the advantages of thin, energy-saving, radiation-free, and is widely applied to, such as, liquid crystal (LC) TV, mobile phone, personal digital assistant (PDA), digital camera, computer monitor or notebook computer monitor, and dominates the tablet display market.
In the known LCDs, the majority is of the backlight type, comprising LCD panel and the backlight module. The operation theory behind the LCD panel is to fill the LC molecules into between a thin film transistor (TFT) array substrate and a color filter (CF) substrate, and apply a driving voltage between the two substrates to control the rotation of the LC molecules to refract the light from the backlight module.
The LCD panel comprises various pixel arrangements of array forms. As the technology progresses, each pixel evolves from comprising a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel to comprising a red (R) sub-pixel, a green (G) sub-pixel, a blue (B) sub-pixel, and a white (W) sub-pixel, also known as WRGB pixel structure. Each sub-pixel is connected to a TFT, and the gate of the TFT is connected to a horizontal scan line, the drain is connected to a data line in the vertical direction and the source is connected to a pixel electrode. When a sufficient voltage is applied to the horizontal scan line, the TFT connected to the scan line will turn on so that the signal voltage on the data line can be written into the sub-pixels to control the transmittance of the LC to achieve displaying.
The known driving method for LCD panel usually comprises: frame inversion mode, line inversion mode and dot inversion mode, wherein the dot inversion mode refer to that, in each frame, each sub-pixel has a voltage parity different from the adjacent surrounding four sub-pixels. In dot inversion mode, the LCD panel suffers the least flicker and crosstalk problems and shows the best displaying result.
In the known manufacturing process for WRGB pixel structure, to reduce the number of pins of source IC and the fan-out lines, a de-multiplexer (demux) is often used in design to allocate a fan-out line to a plurality of data lines, and uses the timing of demux to control the data line of the active area. However, such design results in the plurality of data lines under the control of a fan-out line has the same parity. As the LC realizes frame inversion mode during the parity inversion process, the above design will cause severe flickering in the panel, especially for WRGB pixel structure wherein a fan-out line is allocated to four data lines, often leading to crosstalk situation and severely affecting the display. A common solution is to use a jumper design at the end of the demux to change the scan manner of the gate scan line from column-by-column to turning on the gate lines for odd-numbered columns first, followed by turning on the gate lines for the even-numbered columns. As such, the parity inversion of the panel is changed; however, this solution is not exactly dot inversion by definition.
Refer to FIG. 1. The known LCD panel usually arranges the horizontal gate scan lines with equal intervals between two adjacent lines. For a positive number n, the n-th column TFTs are all located below the corresponding n-th gate scan line G(n). Refer to FIG. 2 the demux 1 controlling the data lines shown in FIG. 1 comprises four routings 11, 12, 13, 14, and a plurality of control switch sets, with each control switch sets comprising four TFTs T100, T200, T300, T400. The gates of the four TFTs of the same control switch set are connected together to a routing, the sources connected together to a fan-out line 2, and the drains connected together to a data line. Two adjacent fan-out lines 2 have the opposite voltage parities. A jumper is used at the end of the demux 1. For two adjacent switch control sets, the drain of the second TFT T200 of the left set jumps to connect the sixth data line D6, the drain of the third TFT T300 of the left set jumps to connect the seventh data line D7, the drain of the second TFT T200 of the right set jumps to connect the second data line D2, the drain of the third TFT T300 of the right set jumps to connect the third data line D3.
In the timing control of FIG. 3, the gate scan lines are scanned line-by-line. Because the four data lines controlled by the same fan-out line 2 have the same voltage parity, the above conventional display effect of the panel is as shown in FIG. 4, wherein the first, fourth, sixth and seventh sub-pixels have positive parity, and the second, third, fifth and eighth sub-pixel have negative parity.
In the timing control of FIG. 5, the odd-numbered gate scan lines of the m-th frame are turned on line-by-line first, following by the even-numbered gate scan lines. As shown in FIG. 6, in two adjacent frames, the voltage parity of the same fan-out line is opposite, and the display effect for two adjacent frames in conventional panel is stacked up as shown in FIG. 7. Although the dot inversion is achieved among each row of pixels, the dot inversion does not show up in each column of pixels. By definition, the strict dot inversion is not achieved.